1 | /* $NetBSD: fwohcireg.h,v 1.18 2010/03/29 03:05:27 kiyohara Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2003 Hidetoshi Shimokawa |
5 | * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa |
6 | * All rights reserved. |
7 | * |
8 | * Redistribution and use in source and binary forms, with or without |
9 | * modification, are permitted provided that the following conditions |
10 | * are met: |
11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the |
15 | * documentation and/or other materials provided with the distribution. |
16 | * 3. All advertising materials mentioning features or use of this software |
17 | * must display the acknowledgement as bellow: |
18 | * |
19 | * This product includes software developed by K. Kobayashi and H. Shimokawa |
20 | * |
21 | * 4. The name of the author may not be used to endorse or promote products |
22 | * derived from this software without specific prior written permission. |
23 | * |
24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
25 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
27 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, |
28 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
32 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
33 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
34 | * POSSIBILITY OF SUCH DAMAGE. |
35 | * |
36 | * $FreeBSD: src/sys/dev/firewire/fwohcireg.h,v 1.24 2009/02/12 03:05:42 sbruno Exp $ |
37 | * |
38 | */ |
39 | #ifndef _FWOHCIREG_H_ |
40 | #define _FWOHCIREG_H_ |
41 | |
42 | #define PCI_CBMEM PCIR_BAR(0) |
43 | |
44 | #define FW_VENDORID_NATSEMI 0x100B |
45 | #define FW_VENDORID_NEC 0x1033 |
46 | #define FW_VENDORID_SIS 0x1039 |
47 | #define FW_VENDORID_TI 0x104c |
48 | #define FW_VENDORID_SONY 0x104d |
49 | #define FW_VENDORID_VIA 0x1106 |
50 | #define FW_VENDORID_RICOH 0x1180 |
51 | #define FW_VENDORID_APPLE 0x106b |
52 | #define FW_VENDORID_LUCENT 0x11c1 |
53 | #define FW_VENDORID_INTEL 0x8086 |
54 | #define FW_VENDORID_ADAPTEC 0x9004 |
55 | #define FW_VENDORID_SUN 0x108e |
56 | |
57 | #define FW_DEVICE_CS4210 (0x000f << 16) |
58 | #define FW_DEVICE_UPD861 (0x0063 << 16) |
59 | #define FW_DEVICE_UPD871 (0x00ce << 16) |
60 | #define FW_DEVICE_UPD72870 (0x00cd << 16) |
61 | #define FW_DEVICE_UPD72873 (0x00e7 << 16) |
62 | #define FW_DEVICE_UPD72874 (0x00f2 << 16) |
63 | #define FW_DEVICE_TITSB22 (0x8009 << 16) |
64 | #define FW_DEVICE_TITSB23 (0x8019 << 16) |
65 | #define FW_DEVICE_TITSB26 (0x8020 << 16) |
66 | #define FW_DEVICE_TITSB43 (0x8021 << 16) |
67 | #define FW_DEVICE_TITSB43A (0x8023 << 16) |
68 | #define FW_DEVICE_TITSB43AB23 (0x8024 << 16) |
69 | #define FW_DEVICE_TITSB82AA2 (0x8025 << 16) |
70 | #define FW_DEVICE_TITSB43AB21 (0x8026 << 16) |
71 | #define FW_DEVICE_TIPCI4410A (0x8017 << 16) |
72 | #define FW_DEVICE_TIPCI4450 (0x8011 << 16) |
73 | #define FW_DEVICE_TIPCI4451 (0x8027 << 16) |
74 | #define FW_DEVICE_CXD1947 (0x8009 << 16) |
75 | #define FW_DEVICE_CXD3222 (0x8039 << 16) |
76 | #define FW_DEVICE_VT6306 (0x3044 << 16) |
77 | #define FW_DEVICE_R5C551 (0x0551 << 16) |
78 | #define FW_DEVICE_R5C552 (0x0552 << 16) |
79 | #define FW_DEVICE_PANGEA (0x0030 << 16) |
80 | #define FW_DEVICE_UNINORTH (0x0031 << 16) |
81 | #define FW_DEVICE_AIC5800 (0x5800 << 16) |
82 | #define FW_DEVICE_FW322 (0x5811 << 16) |
83 | #define FW_DEVICE_7007 (0x7007 << 16) |
84 | #define FW_DEVICE_82372FB (0x7605 << 16) |
85 | #define FW_DEVICE_PCIO2FW (0x1102 << 16) |
86 | |
87 | #define PCI_INTERFACE_OHCI 0x10 |
88 | |
89 | #define PCI_OHCI_MAP_REGISTER 0x10 |
90 | |
91 | #define OHCI_DMA_ITCH 0x20 |
92 | #define OHCI_DMA_IRCH 0x20 |
93 | |
94 | #define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) |
95 | |
96 | |
97 | typedef uint32_t fwohcireg_t; |
98 | |
99 | /* for PCI */ |
100 | #if BYTE_ORDER == BIG_ENDIAN |
101 | #define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) |
102 | #define FWOHCI_DMA_READ(x) le32toh(x) |
103 | #define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) |
104 | #define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) |
105 | #else |
106 | #define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) |
107 | #define FWOHCI_DMA_READ(x) (x) |
108 | #define FWOHCI_DMA_SET(x, y) ((x) |= (y)) |
109 | #define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) |
110 | #endif |
111 | |
112 | struct fwohcidb { |
113 | union { |
114 | struct { |
115 | uint32_t cmd; |
116 | uint32_t addr; |
117 | uint32_t depend; |
118 | uint32_t res; |
119 | } desc; |
120 | uint32_t immed[4]; |
121 | } db; |
122 | #define OHCI_STATUS_SHIFT 16 |
123 | #define OHCI_COUNT_MASK 0xffff |
124 | #define OHCI_OUTPUT_MORE (0 << 28) |
125 | #define OHCI_OUTPUT_LAST (1 << 28) |
126 | #define OHCI_INPUT_MORE (2 << 28) |
127 | #define OHCI_INPUT_LAST (3 << 28) |
128 | #define OHCI_STORE_QUAD (4 << 28) |
129 | #define OHCI_LOAD_QUAD (5 << 28) |
130 | #define OHCI_NOP (6 << 28) |
131 | #define OHCI_STOP (7 << 28) |
132 | #define OHCI_STORE (8 << 28) |
133 | #define OHCI_CMD_MASK (0xf << 28) |
134 | |
135 | #define OHCI_UPDATE (1 << 27) |
136 | |
137 | #define OHCI_KEY_ST0 (0 << 24) |
138 | #define OHCI_KEY_ST1 (1 << 24) |
139 | #define OHCI_KEY_ST2 (2 << 24) |
140 | #define OHCI_KEY_ST3 (3 << 24) |
141 | #define OHCI_KEY_REGS (5 << 24) |
142 | #define OHCI_KEY_SYS (6 << 24) |
143 | #define OHCI_KEY_DEVICE (7 << 24) |
144 | #define OHCI_KEY_MASK (7 << 24) |
145 | |
146 | #define OHCI_INTERRUPT_NEVER (0 << 20) |
147 | #define OHCI_INTERRUPT_TRUE (1 << 20) |
148 | #define OHCI_INTERRUPT_FALSE (2 << 20) |
149 | #define OHCI_INTERRUPT_ALWAYS (3 << 20) |
150 | |
151 | #define OHCI_BRANCH_NEVER (0 << 18) |
152 | #define OHCI_BRANCH_TRUE (1 << 18) |
153 | #define OHCI_BRANCH_FALSE (2 << 18) |
154 | #define OHCI_BRANCH_ALWAYS (3 << 18) |
155 | #define OHCI_BRANCH_MASK (3 << 18) |
156 | |
157 | #define OHCI_WAIT_NEVER (0 << 16) |
158 | #define OHCI_WAIT_TRUE (1 << 16) |
159 | #define OHCI_WAIT_FALSE (2 << 16) |
160 | #define OHCI_WAIT_ALWAYS (3 << 16) |
161 | }; |
162 | |
163 | #define OHCI_SPD_S100 0x4 |
164 | #define OHCI_SPD_S200 0x1 |
165 | #define OHCI_SPD_S400 0x2 |
166 | |
167 | |
168 | #define FWOHCIEV_NOSTAT 0 |
169 | #define FWOHCIEV_LONGP 2 |
170 | #define FWOHCIEV_MISSACK 3 |
171 | #define FWOHCIEV_UNDRRUN 4 |
172 | #define FWOHCIEV_OVRRUN 5 |
173 | #define FWOHCIEV_DESCERR 6 |
174 | #define FWOHCIEV_DTRDERR 7 |
175 | #define FWOHCIEV_DTWRERR 8 |
176 | #define FWOHCIEV_BUSRST 9 |
177 | #define FWOHCIEV_TIMEOUT 0xa |
178 | #define FWOHCIEV_TCODERR 0xb |
179 | #define FWOHCIEV_UNKNOWN 0xe |
180 | #define FWOHCIEV_FLUSHED 0xf |
181 | #define FWOHCIEV_ACKCOMPL 0x11 |
182 | #define FWOHCIEV_ACKPEND 0x12 |
183 | #define FWOHCIEV_ACKBSX 0x14 |
184 | #define FWOHCIEV_ACKBSA 0x15 |
185 | #define FWOHCIEV_ACKBSB 0x16 |
186 | #define FWOHCIEV_ACKTARD 0x1b |
187 | #define FWOHCIEV_ACKDERR 0x1d |
188 | #define FWOHCIEV_ACKTERR 0x1e |
189 | |
190 | #define FWOHCIEV_MASK 0x1f |
191 | |
192 | struct ohci_dma { |
193 | fwohcireg_t cntl; |
194 | |
195 | #define OHCI_CNTL_CYCMATCH_S (0x1 << 31) |
196 | |
197 | #define OHCI_CNTL_BUFFIL (0x1 << 31) |
198 | #define OHCI_CNTL_ISOHDR (0x1 << 30) |
199 | #define OHCI_CNTL_CYCMATCH_R (0x1 << 29) |
200 | #define OHCI_CNTL_MULTICH (0x1 << 28) |
201 | |
202 | #define OHCI_CNTL_DMA_RUN (0x1 << 15) |
203 | #define OHCI_CNTL_DMA_WAKE (0x1 << 12) |
204 | #define OHCI_CNTL_DMA_DEAD (0x1 << 11) |
205 | #define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) |
206 | #define OHCI_CNTL_DMA_BT (0x1 << 8) |
207 | #define OHCI_CNTL_DMA_BAD (0x1 << 7) |
208 | #define OHCI_CNTL_DMA_STAT (0xff) |
209 | |
210 | fwohcireg_t cntl_clr; |
211 | fwohcireg_t dummy0; |
212 | fwohcireg_t cmd; |
213 | fwohcireg_t match; |
214 | fwohcireg_t dummy1; |
215 | fwohcireg_t dummy2; |
216 | fwohcireg_t dummy3; |
217 | }; |
218 | |
219 | struct ohci_itdma { |
220 | fwohcireg_t cntl; |
221 | fwohcireg_t cntl_clr; |
222 | fwohcireg_t dummy0; |
223 | fwohcireg_t cmd; |
224 | }; |
225 | |
226 | struct ohci_registers { |
227 | fwohcireg_t ver; /* Version No. 0x0 */ |
228 | fwohcireg_t guid; /* GUID_ROM No. 0x4 */ |
229 | fwohcireg_t retry; /* AT retries 0x8 */ |
230 | #define FWOHCI_RETRY 0x8 |
231 | fwohcireg_t csr_data; /* CSR data 0xc */ |
232 | fwohcireg_t csr_cmp; /* CSR compare 0x10 */ |
233 | fwohcireg_t csr_cntl; /* CSR compare 0x14 */ |
234 | fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ |
235 | fwohcireg_t bus_id; /* BUS_ID 0x1c */ |
236 | fwohcireg_t bus_opt; /* BUS option 0x20 */ |
237 | #define FWOHCIGUID_H 0x24 |
238 | #define FWOHCIGUID_L 0x28 |
239 | fwohcireg_t guid_hi; /* GUID hi 0x24 */ |
240 | fwohcireg_t guid_lo; /* GUID lo 0x28 */ |
241 | fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ |
242 | fwohcireg_t config_rom; /* config ROM map 0x34 */ |
243 | fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ |
244 | fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ |
245 | fwohcireg_t vender; /* vender ID 0x40 */ |
246 | fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ |
247 | fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ |
248 | fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ |
249 | #define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ |
250 | #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ |
251 | #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ |
252 | #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ |
253 | #define OHCI_HCC_LPS (1 << 19) /* LPS */ |
254 | #define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ |
255 | #define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ |
256 | #define OHCI_HCC_RESET (1 << 16) /* softReset */ |
257 | fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ |
258 | fwohcireg_t dummy3[1]; /* dummy 0x60 */ |
259 | fwohcireg_t sid_buf; /* self id buffer 0x64 */ |
260 | fwohcireg_t sid_cnt; /* self id count 0x68 */ |
261 | fwohcireg_t dummy4[1]; /* dummy 0x6c */ |
262 | fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ |
263 | fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ |
264 | fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ |
265 | fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ |
266 | #define FWOHCI_INTSTAT 0x80 |
267 | #define FWOHCI_INTSTATCLR 0x84 |
268 | #define FWOHCI_INTMASK 0x88 |
269 | #define FWOHCI_INTMASKCLR 0x8c |
270 | fwohcireg_t int_stat; /* 0x80 */ |
271 | fwohcireg_t int_clear; /* 0x84 */ |
272 | fwohcireg_t int_mask; /* 0x88 */ |
273 | fwohcireg_t int_mask_clear; /* 0x8c */ |
274 | fwohcireg_t it_int_stat; /* 0x90 */ |
275 | fwohcireg_t it_int_clear; /* 0x94 */ |
276 | fwohcireg_t it_int_mask; /* 0x98 */ |
277 | fwohcireg_t it_mask_clear; /* 0x9c */ |
278 | fwohcireg_t ir_int_stat; /* 0xa0 */ |
279 | fwohcireg_t ir_int_clear; /* 0xa4 */ |
280 | fwohcireg_t ir_int_mask; /* 0xa8 */ |
281 | fwohcireg_t ir_mask_clear; /* 0xac */ |
282 | fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ |
283 | fwohcireg_t fairness; /* fairness control 0xdc */ |
284 | fwohcireg_t link_cntl; /* Chip control 0xe0*/ |
285 | fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ |
286 | #define FWOHCI_NODEID 0xe8 |
287 | fwohcireg_t node; /* Node ID 0xe8 */ |
288 | #define OHCI_NODE_VALID (1 << 31) |
289 | #define OHCI_NODE_ROOT (1 << 30) |
290 | |
291 | #define OHCI_ASYSRCBUS 1 |
292 | |
293 | fwohcireg_t phy_access; /* PHY cntl 0xec */ |
294 | #define PHYDEV_RDDONE (1<<31) |
295 | #define PHYDEV_RDCMD (1<<15) |
296 | #define PHYDEV_WRCMD (1<<14) |
297 | #define PHYDEV_REGADDR 8 |
298 | #define PHYDEV_WRDATA 0 |
299 | #define PHYDEV_RDADDR 24 |
300 | #define PHYDEV_RDDATA 16 |
301 | |
302 | fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ |
303 | fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ |
304 | fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ |
305 | fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ |
306 | fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ |
307 | fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ |
308 | fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ |
309 | fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ |
310 | fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ |
311 | fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ |
312 | |
313 | fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ |
314 | |
315 | fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ |
316 | |
317 | /* 0x180, 0x184, 0x188, 0x18c */ |
318 | /* 0x190, 0x194, 0x198, 0x19c */ |
319 | /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ |
320 | /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ |
321 | /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ |
322 | /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ |
323 | /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ |
324 | /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ |
325 | struct ohci_dma dma_ch[0x4]; |
326 | |
327 | /* 0x200, 0x204, 0x208, 0x20c */ |
328 | /* 0x210, 0x204, 0x208, 0x20c */ |
329 | struct ohci_itdma dma_itch[0x20]; |
330 | |
331 | /* 0x400, 0x404, 0x408, 0x40c */ |
332 | /* 0x410, 0x404, 0x408, 0x40c */ |
333 | struct ohci_dma dma_irch[0x20]; |
334 | }; |
335 | |
336 | struct fwohcidb_tr { |
337 | int idx; |
338 | STAILQ_ENTRY(fwohcidb_tr) link; |
339 | struct fw_xfer *xfer; |
340 | struct fwohcidb *db; |
341 | bus_dmamap_t dma_map; |
342 | void *buf; |
343 | bus_addr_t bus_addr; |
344 | int dbcnt; |
345 | }; |
346 | |
347 | /* |
348 | * OHCI info structure. |
349 | */ |
350 | struct fwohci_txpkthdr { |
351 | union { |
352 | uint32_t ld[4]; |
353 | struct { |
354 | #if BYTE_ORDER == BIG_ENDIAN |
355 | uint32_t spd:16, /* XXX include reserved field */ |
356 | :8, |
357 | tcode:4, |
358 | :4; |
359 | #else |
360 | uint32_t :4, |
361 | tcode:4, |
362 | :8, |
363 | spd:16; /* XXX include reserved fields */ |
364 | #endif |
365 | } common; |
366 | struct { |
367 | #if BYTE_ORDER == BIG_ENDIAN |
368 | uint32_t :8, |
369 | srcbus:1, |
370 | :4, |
371 | spd:3, |
372 | tlrt:8, |
373 | tcode:4, |
374 | :4; |
375 | #else |
376 | uint32_t :4, |
377 | tcode:4, |
378 | tlrt:8, |
379 | spd:3, |
380 | :4, |
381 | srcbus:1, |
382 | :8; |
383 | #endif |
384 | BIT16x2(dst, ); |
385 | } asycomm; |
386 | struct { |
387 | #if BYTE_ORDER == BIG_ENDIAN |
388 | uint32_t :13, |
389 | spd:3, |
390 | chtag:8, |
391 | tcode:4, |
392 | sy:4; |
393 | #else |
394 | uint32_t sy:4, |
395 | tcode:4, |
396 | chtag:8, |
397 | spd:3, |
398 | :13; |
399 | #endif |
400 | BIT16x2(len, ); |
401 | } stream; |
402 | } mode; |
403 | }; |
404 | struct fwohci_trailer { |
405 | #if BYTE_ORDER == BIG_ENDIAN |
406 | uint32_t stat:16, |
407 | time:16; |
408 | #else |
409 | uint32_t time:16, |
410 | stat:16; |
411 | #endif |
412 | }; |
413 | |
414 | #define OHCI_CNTL_CYCSRC (0x1 << 22) |
415 | #define OHCI_CNTL_CYCMTR (0x1 << 21) |
416 | #define OHCI_CNTL_CYCTIMER (0x1 << 20) |
417 | #define OHCI_CNTL_PHYPKT (0x1 << 10) |
418 | #define OHCI_CNTL_SID (0x1 << 9) |
419 | |
420 | /* |
421 | * defined in OHCI 1.1 |
422 | * chapter 6.1 |
423 | */ |
424 | #define OHCI_INT_DMA_ATRQ (0x1 << 0) |
425 | #define OHCI_INT_DMA_ATRS (0x1 << 1) |
426 | #define OHCI_INT_DMA_ARRQ (0x1 << 2) |
427 | #define OHCI_INT_DMA_ARRS (0x1 << 3) |
428 | #define OHCI_INT_DMA_PRRQ (0x1 << 4) |
429 | #define OHCI_INT_DMA_PRRS (0x1 << 5) |
430 | #define OHCI_INT_DMA_IT (0x1 << 6) |
431 | #define OHCI_INT_DMA_IR (0x1 << 7) |
432 | #define OHCI_INT_PW_ERR (0x1 << 8) |
433 | #define OHCI_INT_LR_ERR (0x1 << 9) |
434 | #define OHCI_INT_PHY_SID (0x1 << 16) |
435 | #define OHCI_INT_PHY_BUS_R (0x1 << 17) |
436 | #define OHCI_INT_REG_FAIL (0x1 << 18) |
437 | #define OHCI_INT_PHY_INT (0x1 << 19) |
438 | #define OHCI_INT_CYC_START (0x1 << 20) |
439 | #define OHCI_INT_CYC_64SECOND (0x1 << 21) |
440 | #define OHCI_INT_CYC_LOST (0x1 << 22) |
441 | #define OHCI_INT_CYC_ERR (0x1 << 23) |
442 | #define OHCI_INT_ERR (0x1 << 24) |
443 | #define OHCI_INT_CYC_LONG (0x1 << 25) |
444 | #define OHCI_INT_PHY_REG (0x1 << 26) |
445 | #define OHCI_INT_EN (0x1 << 31) |
446 | |
447 | #define IP_CHANNELS 0x0234 |
448 | #define FWOHCI_MAXREC 2048 |
449 | |
450 | #define OHCI_ISORA 0x02 |
451 | #define OHCI_ISORB 0x04 |
452 | |
453 | #define FWOHCITCODE_PHY 0xe |
454 | |
455 | #endif /* _FWOHCIREG_H_ */ |
456 | |