1 | /* $NetBSD: i82365reg.h,v 1.10 2005/12/11 12:21:26 christos Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 1997 Marc Horowitz. All rights reserved. |
5 | * |
6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions |
8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
14 | * 3. All advertising materials mentioning features or use of this software |
15 | * must display the following acknowledgement: |
16 | * This product includes software developed by Marc Horowitz. |
17 | * 4. The name of the author may not be used to endorse or promote products |
18 | * derived from this software without specific prior written permission. |
19 | * |
20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
21 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
22 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
23 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
26 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
27 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
30 | */ |
31 | |
32 | /* |
33 | * All information is from the intel 82365sl PC Card Interface Controller |
34 | * (PCIC) data sheet, marked "preliminary". Order number 290423-002, January |
35 | * 1993. |
36 | */ |
37 | |
38 | #define PCIC_IOSIZE 2 |
39 | |
40 | #define PCIC_REG_INDEX 0 |
41 | #define PCIC_REG_DATA 1 |
42 | |
43 | /* |
44 | * The PCIC allows two chips to share the same address. In order not to run |
45 | * afoul of the netbsd device model, this driver will treat those chips as |
46 | * the same device. |
47 | */ |
48 | |
49 | /* pcic can have 2 controllers offset by 0x80 and 2 sockets offset by 0x40 */ |
50 | #define PCIC_CHIP_OFFSET 0x80 |
51 | #define PCIC_SOCKET_OFFSET 0x40 |
52 | |
53 | /* general setup registers */ |
54 | |
55 | #define PCIC_IDENT 0x00 /* RO */ |
56 | #define PCIC_IDENT_IFTYPE_MASK 0xC0 |
57 | #define PCIC_IDENT_IFTYPE_IO_ONLY 0x00 |
58 | #define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40 |
59 | #define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80 |
60 | #define PCIC_IDENT_IFTYPE_RESERVED 0xC0 |
61 | #define PCIC_IDENT_ZERO 0x30 |
62 | #define PCIC_IDENT_REV_MASK 0x0F |
63 | #define PCIC_IDENT_REV_I82365SLR0 0x02 |
64 | #define PCIC_IDENT_REV_I82365SLR1 0x03 |
65 | |
66 | #define PCIC_IDENT_ID_INTEL0 0x82 |
67 | #define PCIC_IDENT_ID_INTEL1 0x83 |
68 | #define PCIC_IDENT_ID_INTEL2 0x84 |
69 | #define PCIC_IDENT_ID_IBM1 0x88 |
70 | #define PCIC_IDENT_ID_IBM2 0x89 |
71 | #define PCIC_IDENT_ID_IBM3 0x8A |
72 | |
73 | #define PCIC_IF_STATUS 0x01 /* RO */ |
74 | #define PCIC_IF_STATUS_GPI 0x80 /* General Purpose Input */ |
75 | #define PCIC_IF_STATUS_POWERACTIVE 0x40 |
76 | #define PCIC_IF_STATUS_READY 0x20 /* really READY/!BUSY */ |
77 | #define PCIC_IF_STATUS_MEM_WP 0x10 |
78 | #define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C |
79 | #define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C |
80 | #define PCIC_IF_STATUS_BATTERY_MASK 0x03 |
81 | #define PCIC_IF_STATUS_BATTERY_DEAD1 0x00 |
82 | #define PCIC_IF_STATUS_BATTERY_DEAD2 0x01 |
83 | #define PCIC_IF_STATUS_BATTERY_WARNING 0x02 |
84 | #define PCIC_IF_STATUS_BATTERY_GOOD 0x03 |
85 | |
86 | #define PCIC_PWRCTL 0x02 /* RW */ |
87 | #define PCIC_PWRCTL_OE 0x80 /* output enable */ |
88 | #define PCIC_PWRCTL_DISABLE_RESETDRV 0x40 |
89 | #define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20 |
90 | #define PCIC_PWRCTL_PWR_ENABLE 0x10 |
91 | #define PCIC_PWRCTL_VPP2_MASK 0x0C |
92 | #define PCIC_PWRCTL_VPP2_RESERVED 0x0C |
93 | #define PCIC_PWRCTL_VPP2_12V 0x08 |
94 | #define PCIC_PWRCTL_VPP2_VCC 0x04 |
95 | #define PCIC_PWRCTL_VPP2_OFF 0x00 |
96 | #define PCIC_PWRCTL_VPP1_MASK 0x03 |
97 | #define PCIC_PWRCTL_VPP1_RESERVED 0x03 |
98 | #define PCIC_PWRCTL_VPP1_12V 0x02 |
99 | #define PCIC_PWRCTL_VPP1_VCC 0x01 |
100 | #define PCIC_PWRCTL_VPP1_OFF 0x00 |
101 | |
102 | #define PCIC_CSC 0x04 /* RO */ |
103 | #define PCIC_CSC_ZERO 0xE0 |
104 | #define PCIC_CSC_GPI 0x10 |
105 | #define PCIC_CSC_CD 0x08 /* Card Detect Change */ |
106 | #define PCIC_CSC_READY 0x04 |
107 | #define PCIC_CSC_BATTWARN 0x02 |
108 | #define PCIC_CSC_BATTDEAD 0x01 /* for memory cards */ |
109 | #define PCIC_CSC_RI 0x01 /* for i/o cards */ |
110 | |
111 | #define PCIC_ADDRWIN_ENABLE 0x06 /* RW */ |
112 | #define PCIC_ADDRWIN_ENABLE_IO1 0x80 |
113 | #define PCIC_ADDRWIN_ENABLE_IO0 0x40 |
114 | #define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */ |
115 | #define PCIC_ADDRWIN_ENABLE_MEM4 0x10 |
116 | #define PCIC_ADDRWIN_ENABLE_MEM3 0x08 |
117 | #define PCIC_ADDRWIN_ENABLE_MEM2 0x04 |
118 | #define PCIC_ADDRWIN_ENABLE_MEM1 0x02 |
119 | #define PCIC_ADDRWIN_ENABLE_MEM0 0x01 |
120 | |
121 | /* this is _not_ available on cirrus chips */ |
122 | #define PCIC_CARD_DETECT 0x16 /* RW */ |
123 | #define PCIC_CARD_DETECT_RESERVED 0xC0 |
124 | #define PCIC_CARD_DETECT_SW_INTR 0x20 |
125 | #define PCIC_CARD_DETECT_RESUME_ENABLE 0x10 |
126 | #define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08 |
127 | #define PCIC_CARD_DETECT_GPI_ENABLE 0x04 |
128 | #define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02 |
129 | #define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01 |
130 | |
131 | /* interrupt registers */ |
132 | |
133 | #define PCIC_INTR 0x03 /* RW */ |
134 | #define PCIC_INTR_RI_ENABLE 0x80 |
135 | #define PCIC_INTR_RESET 0x40 /* active low (zero) */ |
136 | #define PCIC_INTR_CARDTYPE_MASK 0x20 |
137 | #define PCIC_INTR_CARDTYPE_IO 0x20 |
138 | #define PCIC_INTR_CARDTYPE_MEM 0x00 |
139 | #define PCIC_INTR_ENABLE 0x10 |
140 | #define PCIC_INTR_IRQ_MASK 0x0F |
141 | #define PCIC_INTR_IRQ_SHIFT 0 |
142 | #define PCIC_INTR_IRQ_NONE 0x00 |
143 | #define PCIC_INTR_IRQ_RESERVED1 0x01 |
144 | #define PCIC_INTR_IRQ_RESERVED2 0x02 |
145 | #define PCIC_INTR_IRQ3 0x03 |
146 | #define PCIC_INTR_IRQ4 0x04 |
147 | #define PCIC_INTR_IRQ5 0x05 |
148 | #define PCIC_INTR_IRQ_RESERVED6 0x06 |
149 | #define PCIC_INTR_IRQ7 0x07 |
150 | #define PCIC_INTR_IRQ_RESERVED8 0x08 |
151 | #define PCIC_INTR_IRQ9 0x09 |
152 | #define PCIC_INTR_IRQ10 0x0A |
153 | #define PCIC_INTR_IRQ11 0x0B |
154 | #define PCIC_INTR_IRQ12 0x0C |
155 | #define PCIC_INTR_IRQ_RESERVED13 0x0D |
156 | #define PCIC_INTR_IRQ14 0x0E |
157 | #define PCIC_INTR_IRQ15 0x0F |
158 | |
159 | #define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ |
160 | |
161 | #define PCIC_CSC_INTR 0x05 /* RW */ |
162 | #define PCIC_CSC_INTR_IRQ_MASK 0xF0 |
163 | #define PCIC_CSC_INTR_IRQ_SHIFT 4 |
164 | #define PCIC_CSC_INTR_IRQ_NONE 0x00 |
165 | #define PCIC_CSC_INTR_IRQ_RESERVED1 0x10 |
166 | #define PCIC_CSC_INTR_IRQ_RESERVED2 0x20 |
167 | #define PCIC_CSC_INTR_IRQ3 0x30 |
168 | #define PCIC_CSC_INTR_IRQ4 0x40 |
169 | #define PCIC_CSC_INTR_IRQ5 0x50 |
170 | #define PCIC_CSC_INTR_IRQ_RESERVED6 0x60 |
171 | #define PCIC_CSC_INTR_IRQ7 0x70 |
172 | #define PCIC_CSC_INTR_IRQ_RESERVED8 0x80 |
173 | #define PCIC_CSC_INTR_IRQ9 0x90 |
174 | #define PCIC_CSC_INTR_IRQ10 0xA0 |
175 | #define PCIC_CSC_INTR_IRQ11 0xB0 |
176 | #define PCIC_CSC_INTR_IRQ12 0xC0 |
177 | #define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0 |
178 | #define PCIC_CSC_INTR_IRQ14 0xE0 |
179 | #define PCIC_CSC_INTR_IRQ15 0xF0 |
180 | #define PCIC_CSC_INTR_CD_ENABLE 0x08 |
181 | #define PCIC_CSC_INTR_READY_ENABLE 0x04 |
182 | #define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02 |
183 | #define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */ |
184 | #define PCIC_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */ |
185 | |
186 | #define PCIC_CSC_INTR_FORMAT "\177\020" "f\4\4CSC_INTR_IRQ\0" \ |
187 | "b\0RI\0" \ |
188 | "b\1BATTWARN\0" \ |
189 | "b\2READY\0" \ |
190 | "b\3CD\0" |
191 | |
192 | #define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ |
193 | |
194 | /* I/O registers */ |
195 | |
196 | #define PCIC_IO_WINS 2 |
197 | |
198 | #define PCIC_IOCTL 0x07 /* RW */ |
199 | #define PCIC_IOCTL_IO1_WAITSTATE 0x80 |
200 | #define PCIC_IOCTL_IO1_ZEROWAIT 0x40 |
201 | #define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20 |
202 | #define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20 |
203 | #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00 |
204 | #define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10 |
205 | #define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10 |
206 | #define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00 |
207 | #define PCIC_IOCTL_IO0_WAITSTATE 0x08 |
208 | #define PCIC_IOCTL_IO0_ZEROWAIT 0x04 |
209 | #define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02 |
210 | #define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02 |
211 | #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00 |
212 | #define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01 |
213 | #define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01 |
214 | #define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00 |
215 | |
216 | #define PCIC_IOADDR0_START_LSB 0x08 |
217 | #define PCIC_IOADDR0_START_MSB 0x09 |
218 | #define PCIC_IOADDR0_STOP_LSB 0x0A |
219 | #define PCIC_IOADDR0_STOP_MSB 0x0B |
220 | #define PCIC_IOADDR1_START_LSB 0x0C |
221 | #define PCIC_IOADDR1_START_MSB 0x0D |
222 | #define PCIC_IOADDR1_STOP_LSB 0x0E |
223 | #define PCIC_IOADDR1_STOP_MSB 0x0F |
224 | |
225 | /* memory registers */ |
226 | |
227 | /* |
228 | * memory window addresses refer to bits A23-A12 of the ISA system memory |
229 | * address. This is a shift of 12 bits. The LSB contains A19-A12, and the |
230 | * MSB contains A23-A20, plus some other bits. |
231 | */ |
232 | |
233 | #define PCIC_MEM_WINS 5 |
234 | |
235 | #define PCIC_MEM_SHIFT 12 |
236 | #define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT) |
237 | |
238 | #define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT |
239 | #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80 |
240 | #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80 |
241 | #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00 |
242 | #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40 |
243 | #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 |
244 | #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F |
245 | |
246 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0 |
247 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 |
248 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 |
249 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 |
250 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 |
251 | #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F |
252 | |
253 | /* |
254 | * The card side of a memory mapping consists of bits A19-A12 of the card |
255 | * memory address in the LSB, and A25-A20 plus some other bits in the MSB. |
256 | * Again, the shift is 12 bits. |
257 | */ |
258 | |
259 | #define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT |
260 | #define PCIC_CARDMEM_ADDRX_MSB_WP 0x80 |
261 | #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40 |
262 | #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40 |
263 | #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00 |
264 | #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F |
265 | |
266 | #define PCIC_SYSMEM_ADDR0_START_LSB 0x10 |
267 | #define PCIC_SYSMEM_ADDR0_START_MSB 0x11 |
268 | #define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12 |
269 | #define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13 |
270 | |
271 | #define PCIC_CARDMEM_ADDR0_LSB 0x14 |
272 | #define PCIC_CARDMEM_ADDR0_MSB 0x15 |
273 | |
274 | /* #define PCIC_RESERVED 0x17 */ |
275 | |
276 | #define PCIC_SYSMEM_ADDR1_START_LSB 0x18 |
277 | #define PCIC_SYSMEM_ADDR1_START_MSB 0x19 |
278 | #define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A |
279 | #define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B |
280 | |
281 | #define PCIC_CARDMEM_ADDR1_LSB 0x1C |
282 | #define PCIC_CARDMEM_ADDR1_MSB 0x1D |
283 | |
284 | #define PCIC_SYSMEM_ADDR2_START_LSB 0x20 |
285 | #define PCIC_SYSMEM_ADDR2_START_MSB 0x21 |
286 | #define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22 |
287 | #define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23 |
288 | |
289 | #define PCIC_CARDMEM_ADDR2_LSB 0x24 |
290 | #define PCIC_CARDMEM_ADDR2_MSB 0x25 |
291 | |
292 | /* #define PCIC_RESERVED 0x26 */ |
293 | /* #define PCIC_RESERVED 0x27 */ |
294 | |
295 | #define PCIC_SYSMEM_ADDR3_START_LSB 0x28 |
296 | #define PCIC_SYSMEM_ADDR3_START_MSB 0x29 |
297 | #define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A |
298 | #define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B |
299 | |
300 | #define PCIC_CARDMEM_ADDR3_LSB 0x2C |
301 | #define PCIC_CARDMEM_ADDR3_MSB 0x2D |
302 | |
303 | /* #define PCIC_RESERVED 0x2E */ |
304 | /* #define PCIC_RESERVED 0x2F */ |
305 | |
306 | #define PCIC_SYSMEM_ADDR4_START_LSB 0x30 |
307 | #define PCIC_SYSMEM_ADDR4_START_MSB 0x31 |
308 | #define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32 |
309 | #define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33 |
310 | |
311 | #define PCIC_CARDMEM_ADDR4_LSB 0x34 |
312 | #define PCIC_CARDMEM_ADDR4_MSB 0x35 |
313 | |
314 | /* #define PCIC_RESERVED 0x36 */ |
315 | /* #define PCIC_RESERVED 0x37 */ |
316 | /* #define PCIC_RESERVED 0x38 */ |
317 | /* #define PCIC_RESERVED 0x39 */ |
318 | /* #define PCIC_RESERVED 0x3A */ |
319 | /* #define PCIC_RESERVED 0x3B */ |
320 | /* #define PCIC_RESERVED 0x3C */ |
321 | /* #define PCIC_RESERVED 0x3D */ |
322 | /* #define PCIC_RESERVED 0x3E */ |
323 | /* #define PCIC_RESERVED 0x3F */ |
324 | |
325 | /* vendor-specific registers */ |
326 | |
327 | #define PCIC_INTEL_GLOBAL_CTL 0x1E /* RW */ |
328 | #define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0 |
329 | #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08 |
330 | #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04 |
331 | #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02 |
332 | #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01 |
333 | |
334 | #define PCIC_CIRRUS_MISC_CTL_1 0x16 /* RW */ |
335 | #define PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE 0x10 |
336 | |
337 | #define PCIC_CIRRUS_FIFO_CTL 0x17 /* RW */ |
338 | #define PCIC_CIRRUS_FIFO_CTL_EMPTY 0x80 /* I/O read */ |
339 | #define PCIC_CIRRUS_FIFO_CTL_FLUSH 0x80 /* I/O write */ |
340 | |
341 | #define PCIC_CIRRUS_MISC_CTL_2 0x1E /* RW */ |
342 | #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04 |
343 | #define PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE 0x02 |
344 | |
345 | #define PCIC_CIRRUS_CHIP_INFO 0x1F |
346 | #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0 |
347 | #define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20 |
348 | #define PCIC_CIRRUS_CHIP_INFO_REV 0x1F |
349 | |
350 | #define PCIC_CIRRUS_EXTENDED_INDEX 0x2E |
351 | #define PCIC_CIRRUS_EXTENDED_DATA 0x2F |
352 | |
353 | #define PCIC_CIRRUS_EXT_CONTROL_1 0x03 |
354 | #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18 |
355 | |
356 | #define PCIC_CIRRUS_PROD_ID 0x35 /* RO */ |
357 | #define PCIC_CIRRUS_PROD_ID_FAM_MASK 0xF0 |
358 | #define PCIC_CIRRUS_PROD_ID_FAM_PD6729 0x20 |
359 | #define PCIC_CIRRUS_PROD_ID_PROD_MASK 0x0F |
360 | #define PCIC_CIRRUS_PROD_ID_PROD_PD6729 0x00 |
361 | |
362 | #define PCIC_RICOH_REG_CHIP_ID 0x3A |
363 | #define PCIC_RICOH_CHIP_ID_5C296 0x32 |
364 | #define PCIC_RICOH_CHIP_ID_5C396 0xB2 |
365 | #define PCIC_RICOH_REG_MCR2 0x2F |
366 | #define PCIC_RICOH_MCR2_VCC_DIRECT 0x08 |
367 | #define PCIC_RICOH_MCR2_VCC_SEL_MASK 0x01 |
368 | #define PCIC_RICOH_MCR2_VCC_SEL_3V 0x01 |
369 | #define PCIC_RICOH_MCR2_VCC_SEL_5V 0x00 |
370 | |