1/* $NetBSD: pci_intr_machdep.c,v 1.38 2016/07/11 06:14:51 knakahara Exp $ */
2
3/*-
4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. All advertising materials mentioning features or use of this software
46 * must display the following acknowledgement:
47 * This product includes software developed by Charles M. Hannum.
48 * 4. The name of the author may not be used to endorse or promote products
49 * derived from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 */
62
63/*
64 * Machine-specific functions for PCI autoconfiguration.
65 *
66 * On PCs, there are two methods of generating PCI configuration cycles.
67 * We try to detect the appropriate mechanism for this machine and set
68 * up a few function pointers to access the correct method directly.
69 *
70 * The configuration method can be hard-coded in the config file by
71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
72 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
73 */
74
75#include <sys/cdefs.h>
76__KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.38 2016/07/11 06:14:51 knakahara Exp $");
77
78#include <sys/types.h>
79#include <sys/param.h>
80#include <sys/time.h>
81#include <sys/systm.h>
82#include <sys/cpu.h>
83#include <sys/errno.h>
84#include <sys/device.h>
85#include <sys/intr.h>
86#include <sys/kmem.h>
87#include <sys/malloc.h>
88
89#include <dev/pci/pcivar.h>
90
91#include "ioapic.h"
92#include "eisa.h"
93#include "acpica.h"
94#include "opt_mpbios.h"
95#include "opt_acpi.h"
96
97#include <machine/i82489reg.h>
98
99#if NIOAPIC > 0 || NACPICA > 0
100#include <machine/i82093reg.h>
101#include <machine/i82093var.h>
102#include <machine/mpconfig.h>
103#include <machine/mpbiosvar.h>
104#include <machine/pic.h>
105#include <x86/pci/pci_msi_machdep.h>
106#endif
107
108#ifdef MPBIOS
109#include <machine/mpbiosvar.h>
110#endif
111
112#if NACPICA > 0
113#include <machine/mpacpi.h>
114#endif
115
116int
117pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
118{
119 pci_intr_pin_t pin = pa->pa_intrpin;
120 pci_intr_line_t line = pa->pa_intrline;
121 pci_chipset_tag_t ipc, pc = pa->pa_pc;
122#if NIOAPIC > 0 || NACPICA > 0
123 pci_intr_pin_t rawpin = pa->pa_rawintrpin;
124 int bus, dev, func;
125#endif
126
127 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
128 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0)
129 continue;
130 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp);
131 }
132
133 if (pin == 0) {
134 /* No IRQ used. */
135 goto bad;
136 }
137
138 *ihp = 0;
139
140 if (pin > PCI_INTERRUPT_PIN_MAX) {
141 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin);
142 goto bad;
143 }
144
145#if NIOAPIC > 0 || NACPICA > 0
146 KASSERT(rawpin >= PCI_INTERRUPT_PIN_A);
147 KASSERT(rawpin <= PCI_INTERRUPT_PIN_D);
148 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func);
149 if (mp_busses != NULL) {
150 /*
151 * Note: PCI_INTERRUPT_PIN_A == 1 where intr_find_mpmapping
152 * wants pci bus_pin encoding which uses INT_A == 0.
153 */
154 if (intr_find_mpmapping(bus,
155 (dev << 2) | (rawpin - PCI_INTERRUPT_PIN_A), ihp) == 0) {
156 if (APIC_IRQ_LEGACY_IRQ(*ihp) == 0)
157 *ihp |= line;
158 return 0;
159 }
160 /*
161 * No explicit PCI mapping found. This is not fatal,
162 * we'll try the ISA (or possibly EISA) mappings next.
163 */
164 }
165#endif
166
167 /*
168 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
169 * `unknown' or `no connection' on a PC. We assume that a device with
170 * `no connection' either doesn't have an interrupt (in which case the
171 * pin number should be 0, and would have been noticed above), or
172 * wasn't configured by the BIOS (in which case we punt, since there's
173 * no real way we can know how the interrupt lines are mapped in the
174 * hardware).
175 *
176 * XXX
177 * Since IRQ 0 is only used by the clock, and we can't actually be sure
178 * that the BIOS did its job, we also recognize that as meaning that
179 * the BIOS has not configured the device.
180 */
181 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
182 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n",
183 '@' + pin, line);
184 goto bad;
185 } else {
186 if (line >= NUM_LEGACY_IRQS) {
187 aprint_normal("pci_intr_map: bad interrupt line %d\n", line);
188 goto bad;
189 }
190 if (line == 2) {
191 aprint_normal("pci_intr_map: changed line 2 to line 9\n");
192 line = 9;
193 }
194 }
195#if NIOAPIC > 0 || NACPICA > 0
196 if (mp_busses != NULL) {
197 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) {
198 if ((*ihp & 0xff) == 0)
199 *ihp |= line;
200 return 0;
201 }
202#if NEISA > 0
203 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) {
204 if ((*ihp & 0xff) == 0)
205 *ihp |= line;
206 return 0;
207 }
208#endif
209 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n",
210 bus, dev, func, pin, line);
211 aprint_normal("pci_intr_map: no MP mapping found\n");
212 }
213#endif
214
215 *ihp = line;
216 return 0;
217
218bad:
219 *ihp = -1;
220 return 1;
221}
222
223const char *
224pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf,
225 size_t len)
226{
227 pci_chipset_tag_t ipc;
228
229 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
230 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0)
231 continue;
232 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih,
233 buf, len);
234 }
235
236 if (INT_VIA_MSI(ih))
237 return x86_pci_msi_string(pc, ih, buf, len);
238
239 return intr_string(ih & ~MPSAFE_MASK, buf, len);
240}
241
242
243const struct evcnt *
244pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
245{
246 pci_chipset_tag_t ipc;
247
248 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
249 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0)
250 continue;
251 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih);
252 }
253
254 /* XXX for now, no evcnt parent reported */
255 return NULL;
256}
257
258int
259pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
260 int attr, uint64_t data)
261{
262
263 switch (attr) {
264 case PCI_INTR_MPSAFE:
265 if (data) {
266 *ih |= MPSAFE_MASK;
267 } else {
268 *ih &= ~MPSAFE_MASK;
269 }
270 /* XXX Set live if already mapped. */
271 return 0;
272 default:
273 return ENODEV;
274 }
275}
276
277void *
278pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih,
279 int level, int (*func)(void *), void *arg, const char *xname)
280{
281 int pin, irq;
282 struct pic *pic;
283#if NIOAPIC > 0
284 struct ioapic_softc *ioapic;
285#endif
286 bool mpsafe;
287 pci_chipset_tag_t ipc;
288
289 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
290 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0)
291 continue;
292 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx,
293 pc, ih, level, func, arg);
294 }
295
296 if (INT_VIA_MSI(ih)) {
297 if (MSI_INT_IS_MSIX(ih))
298 return x86_pci_msix_establish(pc, ih, level, func, arg,
299 xname);
300 else
301 return x86_pci_msi_establish(pc, ih, level, func, arg,
302 xname);
303 }
304
305 pic = &i8259_pic;
306 pin = irq = APIC_IRQ_LEGACY_IRQ(ih);
307 mpsafe = ((ih & MPSAFE_MASK) != 0);
308
309#if NIOAPIC > 0
310 if (ih & APIC_INT_VIA_APIC) {
311 ioapic = ioapic_find(APIC_IRQ_APIC(ih));
312 if (ioapic == NULL) {
313 aprint_normal("pci_intr_establish: bad ioapic %d\n",
314 APIC_IRQ_APIC(ih));
315 return NULL;
316 }
317 pic = &ioapic->sc_pic;
318 pin = APIC_IRQ_PIN(ih);
319 irq = APIC_IRQ_LEGACY_IRQ(ih);
320 if (irq < 0 || irq >= NUM_LEGACY_IRQS)
321 irq = -1;
322 }
323#endif
324
325 return intr_establish_xname(irq, pic, pin, IST_LEVEL, level, func, arg,
326 mpsafe, xname);
327}
328
329void *
330pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih,
331 int level, int (*func)(void *), void *arg)
332{
333
334 return pci_intr_establish_xname(pc, ih, level, func, arg, "unknown");
335}
336
337void
338pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
339{
340 pci_chipset_tag_t ipc;
341
342 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
343 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0)
344 continue;
345 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie);
346 return;
347 }
348
349 /* MSI/MSI-X processing is switched in intr_disestablish(). */
350 intr_disestablish(cookie);
351}
352
353#if NIOAPIC > 0
354pci_intr_type_t
355pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih)
356{
357
358 if (INT_VIA_MSI(ih)) {
359 if (MSI_INT_IS_MSIX(ih))
360 return PCI_INTR_TYPE_MSIX;
361 else
362 return PCI_INTR_TYPE_MSI;
363 } else {
364 return PCI_INTR_TYPE_INTX;
365 }
366}
367
368static void
369x86_pci_intx_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih)
370{
371 char intrstr_buf[INTRIDBUF];
372 const char *intrstr;
373
374 intrstr = pci_intr_string(NULL, *pih, intrstr_buf, sizeof(intrstr_buf));
375 mutex_enter(&cpu_lock);
376 intr_free_io_intrsource(intrstr);
377 mutex_exit(&cpu_lock);
378
379 kmem_free(pih, sizeof(*pih));
380}
381
382int
383pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **pih)
384{
385 struct intrsource *isp;
386 pci_intr_handle_t *handle;
387 int error;
388 char intrstr_buf[INTRIDBUF];
389 const char *intrstr;
390
391 handle = kmem_zalloc(sizeof(*handle), KM_SLEEP);
392 if (handle == NULL) {
393 aprint_normal("cannot allocate pci_intr_handle_t\n");
394 return ENOMEM;
395 }
396
397 if (pci_intr_map(pa, handle) != 0) {
398 aprint_normal("cannot set up pci_intr_handle_t\n");
399 error = EINVAL;
400 goto error;
401 }
402
403 intrstr = pci_intr_string(pa->pa_pc, *handle,
404 intrstr_buf, sizeof(intrstr_buf));
405 mutex_enter(&cpu_lock);
406 isp = intr_allocate_io_intrsource(intrstr);
407 mutex_exit(&cpu_lock);
408 if (isp == NULL) {
409 aprint_normal("can't allocate io_intersource\n");
410 error = ENOMEM;
411 goto error;
412 }
413
414 *pih = handle;
415 return 0;
416
417error:
418 kmem_free(handle, sizeof(*handle));
419 return error;
420}
421
422/*
423 * Interrupt handler allocation utility. This function calls each allocation
424 * function as specified by arguments.
425 * Currently callee functions are pci_intx_alloc(), pci_msi_alloc_exact(),
426 * and pci_msix_alloc_exact().
427 * pa : pci_attach_args
428 * ihps : interrupt handlers
429 * counts : The array of number of required interrupt handlers.
430 * It is overwritten by allocated the number of handlers.
431 * CAUTION: The size of counts[] must be PCI_INTR_TYPE_SIZE.
432 * max_type : "max" type of using interrupts. See below.
433 * e.g.
434 * If you want to use 5 MSI-X, 1 MSI, or INTx, you use "counts" as
435 * int counts[PCI_INTR_TYPE_SIZE];
436 * counts[PCI_INTR_TYPE_MSIX] = 5;
437 * counts[PCI_INTR_TYPE_MSI] = 1;
438 * counts[PCI_INTR_TYPE_INTX] = 1;
439 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX);
440 *
441 * If you want to use hardware max number MSI-X or 1 MSI,
442 * and not to use INTx, you use "counts" as
443 * int counts[PCI_INTR_TYPE_SIZE];
444 * counts[PCI_INTR_TYPE_MSIX] = -1;
445 * counts[PCI_INTR_TYPE_MSI] = 1;
446 * counts[PCI_INTR_TYPE_INTX] = 0;
447 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX);
448 *
449 * If you want to use 3 MSI or INTx, you can use "counts" as
450 * int counts[PCI_INTR_TYPE_SIZE];
451 * counts[PCI_INTR_TYPE_MSI] = 3;
452 * counts[PCI_INTR_TYPE_INTX] = 1;
453 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSI);
454 *
455 * If you want to use 1 MSI or INTx (probably most general usage),
456 * you can simply use this API like
457 * below
458 * error = pci_intr_alloc(pa, ihps, NULL, 0);
459 * ^ ignored
460 */
461int
462pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps,
463 int *counts, pci_intr_type_t max_type)
464{
465 int error;
466 int intx_count, msi_count, msix_count;
467
468 intx_count = msi_count = msix_count = 0;
469 if (counts == NULL) { /* simple pattern */
470 msi_count = 1;
471 intx_count = 1;
472 } else {
473 switch(max_type) {
474 case PCI_INTR_TYPE_MSIX:
475 msix_count = counts[PCI_INTR_TYPE_MSIX];
476 /* FALLTHROUGH */
477 case PCI_INTR_TYPE_MSI:
478 msi_count = counts[PCI_INTR_TYPE_MSI];
479 /* FALLTHROUGH */
480 case PCI_INTR_TYPE_INTX:
481 intx_count = counts[PCI_INTR_TYPE_INTX];
482 break;
483 default:
484 return EINVAL;
485 }
486 }
487
488 if (counts != NULL)
489 memset(counts, 0, sizeof(counts[0]) * PCI_INTR_TYPE_SIZE);
490 error = EINVAL;
491
492 /* try MSI-X */
493 if (msix_count == -1) /* use hardware max */
494 msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag);
495 if (msix_count > 0) {
496 error = pci_msix_alloc_exact(pa, ihps, msix_count);
497 if (error == 0) {
498 KASSERTMSG(counts != NULL,
499 "If MSI-X is used, counts must not be NULL.");
500 counts[PCI_INTR_TYPE_MSIX] = msix_count;
501 goto out;
502 }
503 }
504
505 /* try MSI */
506 if (msi_count == -1) /* use hardware max */
507 msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag);
508 if (msi_count > 0) {
509 error = pci_msi_alloc_exact(pa, ihps, msi_count);
510 if (error == 0) {
511 if (counts != NULL)
512 counts[PCI_INTR_TYPE_MSI] = msi_count;
513 goto out;
514 }
515 }
516
517 /* try INTx */
518 if (intx_count != 0) { /* The number of INTx is always 1. */
519 error = pci_intx_alloc(pa, ihps);
520 if (error == 0) {
521 if (counts != NULL)
522 counts[PCI_INTR_TYPE_INTX] = 1;
523 }
524 }
525
526 out:
527 return error;
528}
529
530void
531pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count)
532{
533 if (pih == NULL)
534 return;
535
536 if (INT_VIA_MSI(*pih)) {
537 if (MSI_INT_IS_MSIX(*pih))
538 return x86_pci_msix_release(pc, pih, count);
539 else
540 return x86_pci_msi_release(pc, pih, count);
541 } else {
542 KASSERT(count == 1);
543 return x86_pci_intx_release(pc, pih);
544 }
545
546}
547#endif
548