1/* $NetBSD: i82802reg.h,v 1.4 2010/08/23 02:57:19 jakllsch Exp $ */
2
3/*
4 * Copyright (c) 2000 Michael Shalayeff
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * Intel 82802AB/82802AC Firmware Hub
31 *
32 * see: ftp://download.intel.com/design/chipsets/datashts/29065804.pdf
33 * and http://www.intel.com/design/chipsets/datashts/29065804.pdf
34 */
35
36/*
37 * MMIO bases and sizes
38 */
39#define I82802AC_REGBASE 0xffb00000
40#define I82802AC_MEMBASE 0xfff00000
41#define I82802AC_WINSIZE 0x00100000
42#define I82802AB_MEMBASE 0xfff80000
43#define I82802AB_WINSIZE 0x00080000
44
45#define I82802_MFG 0x89
46#define I82802AB_ID 0xad
47#define I82802AC_ID 0xac
48
49/*
50 * Intel FWH registers
51 */
52#define I82802_T_BLOCK_LK 0xf0002
53#define I82802_T_MINUS01_LK 0xe0002
54#define I82802_T_MINUS02_LK 0xd0002
55#define I82802_T_MINUS03_LK 0xc0002
56#define I82802_T_MINUS04_LK 0xb0002
57#define I82802_T_MINUS05_LK 0xa0002
58#define I82802_T_MINUS06_LK 0x90002
59#define I82802_T_MINUS07_LK 0x80002
60
61#define I82802_T_MINUS08_LK 0x70002
62#define I82802_T_MINUS09_LK 0x60002
63#define I82802_T_MINUS10_LK 0x50002
64#define I82802_T_MINUS11_LK 0x40002
65#define I82802_T_MINUS12_LK 0x30002
66#define I82802_T_MINUS13_LK 0x20002
67#define I82802_T_MINUS14_LK 0x10002
68#define I82802_T_MINUS15_LK 0x00002
69
70#define I82802_GPI_REG 0xc0100
71
72#define I82802_RNG_HSR 0xc015f /* Hardware Status */
73#define I82802_RNG_DSR 0xc0160 /* Data Status */
74#define I82802_RNG_DR 0xc0161 /* Data */
75
76/*
77 * T_BLOCK_LK and T_MINUS_* (block locking registers)
78 * (table 4-5)
79 */
80#define I82802_BLR_RD 0x04
81#define I82802_BLR_LD 0x02
82#define I82802_BLR_WL 0x01
83
84/*
85 * General Purpose Inputs Register
86 * (table 4-7)
87 */ /* PLCC32/TSOP40 pin # */
88#define I82802_GPI_REG_FGPI4 0x10 /* 30 / 7 */
89#define I82802_GPI_REG_FGPI3 0x08 /* 3 / 15 */
90#define I82802_GPI_REG_FGPI2 0x04 /* 4 / 16 */
91#define I82802_GPI_REG_FGPI1 0x02 /* 5 / 17 */
92#define I82802_GPI_REG_FGPI0 0x01 /* 6 / 18 */
93
94/*
95 * RNG registers
96 */
97#define I82802_RNG_HSR_PRESENT 0x40
98#define I82802_RNG_HSR_ENABLE 0x01
99#define I82802_RNG_DSR_VALID 0x01
100